Ich trau mich ja kaum es zu schreiben, aber gibt es hier Leuts die in nem Betrieb sind und dort Ausbildungen zur IT-Systemintegration anbieten? Ich suche ab August nach was neuem. Master Lehramt will nicht so klappen wie ich wollte.

Yesterday I verified my experiments at .
- Keeping the oscillator warm and cozy helps with clock drift
- The setup puts about 18dBm/63mW into the antenna (at 1GHz, spectrum analyzer can't go higher)
- Just enough to leave a mark on the waterfall

Results of this weekends experiments:
- The LNA works as a <1W PA
- Pointing my old wifi antenna in roughly the right direction is good enough
- My SDR drifts too much
- I can get a barley audible SSTV signal through the transponder (not enough for decoding.)

Was sagt der Baggerfahrer wenn er ein Kabel angräbt?

"Was tut denn ein Kabel wie du in einem Loch wie diesem?"

The first ZX Spectrum prototype. This is what stuff looks like while being developed. Don’t forget that or fear it. It’s easy to forget in an age when we only ever see the shiny façades of technology – whether that’s hardware or software. No one gets it right from the start, it’s always messy, always iterative and you never have all the answers and, heck, half the challenge is figuring out whether you’re even asking the right questions to begin with.


But why are we getting exactly 16Mhz - 10MHz = 6MHz?

No. Somewhere in the sampling circuit there is a conjunction (logical and) between the external clock and the system clock. That's the logic equivalent of multiplying the two. So I've basically build a crude mixer with lots of harmonics giving me f_clock - f_samp (and f_clock + f_samp).

However there is one small detail that's a off:
The Atmega only counted 3000 pulses,
which would be equal to 6MHz.
The "spectrum analyzer" (HP8922E) says my clock is pretty much spot on 10MHz.

So here is what's happening:
The Atmega samples the external clock input once in each system clock cycle.
So I'm stuck with f_samp = 16Mhz.
Sampling theorem tells me I can sample at most f_samp/2 = 8Mhz without aliasing.

So the basic idea was:
1. TCXO -> Si5153 -> 10MHz -> Atmega external timer clock
2. GPS (Ublox Neo-8M) -> 200Hz -> Atmega input capture pin
3. Find an algorithm to tweak the Si5153s parameters until the input counter counts exactly 50000 pulses over a longer period of time

I know that only frequency locks my PLL but according to my guesstimates it should get the error below what I can measure. (I have access to a gps disciplined rubidium normal, but no good frequency counter.)


First QSO via #Eshail2 #QO100 satellite on 25.2.2018 18:30 UTC. Contact was made with @DL6AST in CW mode during my initial test settings .
TX setup: SDRAngel SW, HackRF, LNA, EDUP 8W WiFi Booster, cheap 17el WiFi yagi antenna, 80 cm dish. Next, I'll try without a dish.

🐦🔗: twitter.com/S59MZ/status/11022

Meh ... now it happened. I started buying stuff to build a station for Es'hailSat.

On the bright side if I stick to transmitting for now, I already have an old wifi-antenna with a large reflector is confirmed working as TX-antenna and a rad1o which can do the 2,4GHz.
So all I need is the "8w wifi booster" which is cheap on ebay.

Okay they responded to my review rather quickly, cleaning up all the inconsistencies and explaining some parts of their code that I found suspicious.
Having that as comments would be nice ... but as I said my code is also far from optimal so I can't really complain.

Also they sort of apologized for the profanities and restored the old names. (Even did a rebase and force push to get them out of the history.)

Result looks almost mergeable.

Just got my first pull request on github.
It's for an embedded display driver I wrote, used exactly once and the forgot about.

First glance: Nicely structured different commits, each commit doing one thing only.

Second glance: No description whatsoever, barely any comments (to be fair my code isn't really well documented either) and some of the registers set by the added code contradict themselves.

Third glance:
One commit replaces various occurrences of fck with fuck and clock with cock.. 🤦‍♂️

Oha.. @ulrichkelber hat sich zur Urheberrechtsreform geäußert und dabei sehr kurz und prägnant das Problem an und die damit verbundenen Implikationen für den Datenschutz erklärt.


Hi networking filter bubble, does any have an old IOS image for an old Cisco Catalyst 2950 Switch? Somebody tried to something smart and wiped everything but the bootloader. Sticker on the back says WS-C2950-48-EI

Does anyone here have access to EN 13757-4 (Wireless M-Bus specification)? I'd really appreciate it if I could borrow a copy.

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